The present invention relates to information processing apparatus, such as minicomputers that are controlled by micro instructions, and more specifically to information processing apparatus suitable for high-speed reading of a large number of micro instructions and for fabricating the system into a VLSI circuit.
The commonly used configuration of the conventional apparatus is shown in FIG. 14. The apparatus of this kind is introduced in the IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, October (1984), pp 663-674. The conventional apparatus consists of a basic processing unit (BPU) 14002 for decoding and executing instructions, a RAM 14001 called a control storage (CS) for storing micro instructions, and a main memory 14003. In the figure, 14004 denotes an address bus for micro instructions, 14005 a bus for reading the micro instructions, 14006 an address bus for the main memory, and 14007 a data bus. The capacity of the micro instructions is about 8 to 16k words. The micro instruction is read out normally once for every machine cycle and is decoded and used for controlling the computing device in the BPU. The machine cycle is the fundamental unit of duration for operation that determines the performance of the computer and the time needed for reading the micro instructions often becomes a critical factor for determining the machine cycle.
Another example of the conventional apparatus is given in the Japanese Patent Laid-Open No. 95446/1986. This is a logic circuit which consists of a selection section that selectively switches between a first micro instruction stored in the control storage and a second micro instruction supplied from an external circuit, and a signal processing section that is controlled by the first or second micro instruction. This apparatus lacks design considerations in three points high-speed reading of the micro instructions, reduction in the number of pins, and correction of micro instructions.
With the advance of LSI technology and increased circuit density, it has become possible to fabricate the basic processing unit (BPU) in one chip. The delay time of the logic gates that constitute the LSI has decreased to below 1 ns, thus contributing significantly to a shortening of the machine cycle. The International Solid State Circuits Conference of 1986 introduced a circuit which achieves a the machine cycle of 60 MHz (17 ns) by combining bipolar transistors and MOS transistors at the basic circuit level to take advantage of the high signal speed of the bipolar transistor and the high circuit density and low power consumption of the MOS transistor.
However, the high speed obtained as a result of large scale integration is only effective when the signal is confined within the chip and the delay can be as large as 10 ns to 20 ns when the signal is transferred between chips. In other words, while the speed at which signal is transferred between the logic gates in the one and the same chip is greatly increased, there is a limit to a reduction in the signal transfer time between the chips. This is because the load capacity of the logic gates in the chip reduces as the circuit density increases, whereas the package capacity and the wiring capacity connecting the packages on a printed circuit card remain almost unchanged. Thus, if the control storage (CS) is formed using a RAM different from the chip of the basic processing unit (BPU) according to the conventional configuration, signal transfer occurs between the chips and improvement in the machine cycle is limited. Moreover, since the micro instruction usually has a width of about 64 bits, connection of the BPU to both the memory bus and the micro instruction bus results in a significant increase in the number of pins of the BPUs.
On the other hand, if as in a microprocessor the micro instructions are stored in the on-chip ROM, there is no signal transfer between LSIs, allowing reduction in the machine cycle. However, the capacity of the ROM that can be built on the chip is only 2k words to 4k words and it is not possible to store on the chip all of the large number of micro instructions that are necessary to form a minicomputer. This method has another problem that, if the BPU is manufactured with a ROM as an LSI, an error in the micro instruction cannot easily be corrected.